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The IBM 1130

beating heart animation Photo of IBM 1130 CPU beating heart animation
IBM 1442 Card Reader/Punch IBM 1130 CPU IBM 1132 Printer
IBM 1442
Card Reader/Punch
IBM 1130
Central Processing Unit
IBM 1132
Printer


This is the little machine started it all for me. The system was installed in my high school around the end of 1972, during my Freshman year. In 1973 I took my first computer class (Data Processing 101) and from that point on I was addicted. I learned the basics of computing technology and was instructed in a language called SL1 (Student Language 1) which was a subset of P/L 1 (Programming Language 1). I came back with my first program written and punched before the instructor had even had a chance to i nstall the compiler on the system. With a little instruction I installed it for him and off I went. Looking back it's hard to believe that people were able to do anything useful with such a machine, but back then, when it was the state of the art in computing technology, you couldn't remember how you survived without it.

The IBM 1130 was introduced in 1965 and is considered an early third generation computer. It was a single user batch system and the primary input device was the IBM 1442 card reader which could read 300 cards per minute. The primary output device was the IBM 1132 printer which had a top speed of 80 lines per minute. Shortly after I graduated the printer was replaced with an IBM 1403 printer which had a blazzingly fast top speed of 600 lines per minute. The system console, which was attached to the CPU could also be used for input and output, but this was just a modified IBM Selectric typewriter and had a top speed of about 5 characters second. The IBM 1442 was also capable of being used as an output device and could punch 120 cards per minute.

The maximum amount of addressable memory for the IBM 1130 was 16K (16 bit words) and the system that my high school had contained only 8K. The system had only one disk drive and the disk cartridge that it used contained one platter about the size of a large pizza and was capable of holding about one million characters.

All of the CPU's math was performed using the 16 bit accumulator which also had a extension of another 16 bits that could be used to handle larger computations. All of the arithmetic was done in integer mode and there was no hardware floating point. If you needed to use floating point arithmetic you had to call a software subroutine. The range of integer values for single precision integer arithmetic was -32,768 to +32,767.

The CPU also had three index registers which could be used to modify the base memory address referenced by an instruction. Well, it actually had four index registers but the first (XR0, index register 0) was also the IAR (Instruction Address Register) which pointed to the next instruction in memory to be execute. A subset of the CPU's instruction set was used to place values into the index registers, modify them and store them.

If you're interested, here's the instruction set as I remember it:


LD Load accumulator (from memory)
LDD Load double (accumulator and extension)
STO Store accumulator (to memory)
STD Store double
A Add
AD Add double
S Subtract
SD Subtract double
M Multiply
D Divide
AND Boolean And
OR Boolean Or
EOR Boolean Exclusive Or
LDX Load index register
MDX Modify index register
STX Store index register
SLA Shift left accumulator
SLT Shift left together (accumulator and extension)
SLCA Shift left and count accumulator
SLC Shift left together and count
SRA Shift right accumulator
SRT Shift right together
RTE Rotate right (accmulator and extension)
BSC Branch or skip on condition
BSI Branch and store IAR (Instruction Address Register)
XIO Execute input/output
NOP No operation
LDS Load Status
STS Store Status
WAIT Wait

I know I am missing some because I've only listed 30 and 5 bits were used for the operation code which means there should be 32 of them. Let's see how long it takes for the net to fill in the rest.

LDS, STS and WAIT were added on 29-May-1998 courtesy of Oscar E. Wyss.

Operation
Code
Long
Bit
Index
Register
Modifier
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Most instructions could be executed in "short" (16 bit instruction) or "long" (32 bit instruction) mode. If the instruction was executed in "short" mode then the memory address that it was addressing had to be within -128 or +127 "words" of the instruction itself, the secord half of the instruction contained the relative offset to the address of the operand from the instruction address. If an instruction was executed in "long" mode then the second word contained the absolute address of the operand. When an instrction was execute in long mode the second half of the first word was used as a modified to the base address referenced by the second word. Additionally, long instructions could be executed in "indirect" mode which meant that the address referenc ed by the second word of the instruction contained the actual address (or pointer to) the actual operand. Indirect instructions were flagged by turning on the sign bit (bit 0) in the second word of the "long" instruction.

Trying to debug a program (assembly/machine language) on the 1130 was a real chore. You had to sit at the console and single step through the instructions one by one, checking the contents of the accumulator, extension and various index registers after each step. This would not have been so bad if all of the little light bulbs in these displays were guaranteed to be working all of the time, but frequently some of them were not and you had to guess.

Please be aware that all of this is from memory, and memory that has not been accessed in a very, very long time. In spite of the age of these memories the PARITY CHECK light did not come on a single time while accessing them so most of the information should be reasonably accurate.

1130 Club Card

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